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- Modeling and Analysis of Single Event Effects

in modern device technology creates specific challenges for high fidelity radiation effects modeling of these phenomena while the reduction of feature sizes has made the accurate modeling of SEE and other radiation effects of critical importance These include the need for modeling Soft Error Rates SER Multi Bit Upsets MBU chip packaging and detailed single event effects modeling at the device and circuit level What attendees will learn Why understanding SEE is important Basic Mechanisms Destructive Single Events Effects Modeling and Analysis TCAD Tool Flow Device Techniques for Increasing Resiliency to SEE Non Destructive Single Event Effects Modeling and Analysis TCAD and EDA Tool Flow Device and Circuit Techniques for Reducing Non Destructive SEE System Methodology Examples for a DC DC Boost Converter Power Diode and Logic Block with Quenching Presenter Dr Christopher Nicklaw Chief Engineer at Silvaco s Aerospace Defense unit has over 35 years of experience working on radiation effects in materials He has been involved in both Military and Commercial systems exposed to radiation environments providing methods in modeling simulation analysis and design at the device circuit and systems level Dr Nicklaw received his B S in Electrical Engineering from Georgia Institute of Technology an M S

Original URL path: http://www.silvaco.fr/webinar/modeling_and_analysis_of_single_event_effects_webinar_bn.html (2016-05-03)

Open archived version from archive - Generally Applicable Degradation Model for Silicon MOS Devices

function with parameters derived from the Spherical harmonic expansion solution to the Boltzmann transport equation This approximation was made to improve calculation speed The Atlas implementation of the BTE solver is sufficiently rapid that a further approximation of the carrier distribution function is not necessary The BTE solver is based on the formulation of Ventura et al 5 The equation for the zeroth order expansion fo of the carrier distribution function is 15 where E is energy in eV g E is the density of states in m 3 eυ 1 F is field in V m τ E is a scattering lifetime in seconds u g is the group velocity in m s c op is optical phonon scattering coefficient in m 3 J s N op is the optical phonon occupation number and the optical phonon energy is ω in eV N is the optical phonon occupation number plus one simplified as follows 16 where K b is Boltzmanns constant and T 1 is the lattice temperature The first order expansion f 1 is then obtained from 17 The lifetime E is derived from the carrier scattering mechanisms Scattering mechanisms which are included by default are optical phonon scattering acoustic phonon scattering and ionized impurity scattering Impact ionization scattering can also be included if required Quantities such as carrier density drift velocity and energy can be calculated from the carrier distribution functions For example the drift velocities as a function of homogeneous field are shown in Figure 1 for electrons and Figure 2 for holes Results are shown for three different values of dopant concentration Figure 1 Homogeneous velocity field curves for electrons Figure 2 Homogeneous velocity field curves for holes To initialize Atlas for solving the BTE the flags BTE PP E for electrons and BTE PP H for holes must be set on the MODELS statement After the BTE has been solved for a specific bias set Atlas includes the acceleration integrals when it saves the structure to file See the Atlas manual 1 for more details on the BTE solver Implementation of the General Framework Model An Atlas device is biased to the stressing configuration using the drift diffusion or energy balance models A SOLVE statement with the flags DEVDEG GF E for electrons and DEVDEG GF H for holes will solve the Boltzmann transport equation Up to 10 degradation times can be simulated using the parameters TD1 TD10 on the SOLVE statement The interface charge densities are calculated using equations 1 2 12 and 13 for each requested degradation time and the results are written to a structure file For example the Atlas statement SOLVE DEVDEG GF E TD1 1 0e 2 TD2 1 0e 1 TD3 1 0 TD4 10 0 TD5 1 0e2 OUTFILE simstd str will result in files simstd 1 00e 02s str simstd 1 00e 01s str simstd 1 00e 00s str simstd 1 00e 01s str simstd 1 00e 02s str being written out each having an interface charge density corresponding to the simulated degradation time Example Simple MOSFET The first example is for the MOSFET structure shown in Figure 3 Each of the three different degradation models are looked at in turn for the case of electrons in this device The MP Keldysh cross section σ e mp 0 was set to zero and the SP Keldysh cross section was set to be 1 0 10 22 cm 2 with a threshold energy of 2 2 eV The saturated dangling bond density Nasp was set to 4 10 12 cm 2 With a gate bias of 2 V a BTE solution was obtained at a drain voltage of 2 V and also at a drain Voltage of 4 V The acceleration integral for the SP process is shown in Figure 4 for 2V Drain bias and Figure 5 for 4V Drain bias At 4V drain bias it is many orders of magnitude larger than at 2V drain bias In Figure 6 the first order component of the electron distribution function is plotted at the node where the SP acceleration integral is a maximum The electron distribution function at 4V drain bias is much larger at higher energies than the equivalent distribution at 2V drain bias The energy threshold in the calculation of acceleration integral is 2 2 eV and clearly the electron distribution function at 4V drain bias is much larger above this energy Figure 3 Example structure Figure 4 SP Acceleration integral at 2V drain bias logarithmic scale Figure 5 SP Acceleration integral at 4V drain bias logarithmic scale Figure 6 First order component of electron distribution function The simulation was performed with degradation times of 10 milliseconds 100 milliseconds 1 second 10 seconds and 100 seconds The threshold Voltage after each simulation time was calculated from the Gate bias required to achieve a specified drain current and the threshold Voltage shifts calculated At 2V drain bias there was negligible threshold voltage shift and so the calculation was performed with drain biases of 3V and 4V with the resulting shifts being shown in Figure 7 Figure 7 Threshold Voltage shifts due to SP process as a function of stressing time In order to study the MP process in isolation the SP Keldysh cross section σ e sp 0 was set to zero and the MP Keldysh cross section σ e mp 0 was set to be 1 0 10 13 cm 2 with default values for other parameters including a threshold energy of 1 eV The default parameters give a value of P emi of approximately 0 036 second and so at 100 seconds the time evolution will be essentially complete The saturated dangling bond density N was set to 1 10 13 cm 2 With a gate bias of 2 V a BTE solution was obtained at a drain voltage of 2 V and also at a drain Voltage of 4 V The MP Acceleration integral is shown in Figures 8 and 9 for these

Original URL path: http://www.silvaco.fr/tech_lib_TCAD/simulationstandard/2014/apr_may_jun/a1/a1.html (2016-05-03)

Open archived version from archive - Simulating Radiation-Induced Shifts in MOSFET Threshold Voltage

pairs that survive the geminate recombination process drift apart under the influence of the field Insulator charging occurs when some of these carriers become trapped by impurities or other crystal defects present within the insulator material The magnitude of this charging is determined by a balance between carrier capture and emission processes The capture process for insulator traps is the same as for traps in ordinary semiconductors but the emission process appears to be different According to the model of Kimpton and Kerr 3 the primary energy source stimulating the detrapping process is the geminate recombination of electron hole pairs during irradiation As illustrated in Figure 1 a geminate recombination event emits a quantum of energy that may prompt the emission of a hole from a donor like trap or the emission of an electron from an acceptor like trap Meanwhile the trap energies are assumed to be far from the band edges so the ordinary thermally stimulated emission processes are negligible According to these assumptions donor like insulator traps emit holes at the rate where G 0 is the generation factor with units of generated pairs cm3 rad δ is the dose rate in rad s Y is the geminate yield V ϕ is the emission interaction volume for a trap N t is the density of traps and f is the probability that a trap is filled The expression for the emission of electrons from acceptor like traps is similar Breaking down the rate equation G 0 δ is the rate of electron hole pair creation per unit volume 1 Y is the fraction of pairs that undergo geminate recombination and V ϕ N t f is the probability that a phonon created by a geminate recombination event will interact with a filled trap to empty it Simulation To demonstrate the effects of insulator charging due to exposure to high energy radiation we shall use Victory Device to simulate an n MOSFET that is bombarded by x rays The structure and doping of the MOSFET are typical as shown in Figure 3 Figure 3 n MOSFET structure used in simulation of radiation effects In Victory Device the radiation models only apply to semiconductors Consequently to model radiation effects in an insulator you must tell Victory Device to regard the material as a semiconductor To do this set the SEMICONDUCTOR flag on an appropriate MATERIAL statement You may also need to define a limited number of semiconductor properties for the material For this simulation we set the following Semiconductor properties for oxide MATERIAL MATERIAL oxide NC300 2e19 NV300 2e19 EG300 9 SEMICONDUCTOR MATERIAL MATERIAL oxide MUN 1 MUP 1e 3 MATERIAL MATERIAL oxide M VTHP 1 We also specify the following traps in the insulator body and on its interface with the semiconductor These will become charged as the device is irradiated Conditions for radiation induced oxide charging INTOXIDECHARGING R1MATERIAL oxide R2MATERIAL silicon JMODEL P NT P 3e12 SIGMAT P 1 5e 13 SIGMAN P 1e 30 SIGMAPH P

Original URL path: http://www.silvaco.fr/tech_lib_TCAD/simulationstandard/2014/oct_nov_dec/a1/a1.html (2016-05-03)

Open archived version from archive - The Physics of Single Event Burnout (SEB)

self heating effects transforming the secondary stable high current state towards a lower current density The curve from Figure 1 shows that if the diode was biased at 3500 volts a current of approximately 5 amps would be required to initiate a stable self sustaining on state Extrapolating from SEU current curves versus LET energy discussed later in this article this would require a strike with an LET value of over a thousand MeV cm2 mg which is not a likely event The usefulness of this constant temperature I V curve is that it defines one of the two operating boundary conditions In this case the boundary condition being where no self heating occurs Now let us define the other boundary condition where the current from an SEU strike continues for sufficient time such that localized thermal equilibrium occurs Figure 2 shows the original constant temperature curve of Figure 1 but this time over lays the I V curve simulated with the localized self heating model activated Since this is a DC bias sweep then at each point of the I V curve thermal equilibrium has been established Figure 2 Comparing the no self heating with a thermal equilibrium curve Figure 2 immediately shows how vulnerable a power PiN diode could be when the effects of self heating are taken into account Now a sustained current of only tens of micro Amps is required at higher reverse bias voltage in order for a self sustaining thermal runaway event to occur The required current for thermal runaway rapidly increases at lower bias voltages giving rise to the expected behavior that an SEB event is more likely at high reverse bias voltages or saying the same thing in another way an SEU with a higher value of LET is required at lower bias voltages in order to trigger an SEB event Figure 3 shows the temperature at two significant regions in the device the red curve showing the metallurgic junction temperature and green curve at the intrinsic to N boundary It should be noted that the heat sink was defined as coinciding with the anode contact which is the closet to the metallurgic junction which is why metallurgic boundary curve has a lower temperature Figure 3 Temperatures inside the PiN diode at the metallurgic junction and at the N to intrinsic boundary Since in a transient SEU strike thermal equilibrium is not usually obtained we now know our realistic I V curve will trace a path somewhere between these two extremes The most useful predictor of device behavior is therefore to emulate I V curves that show a more realistic current temperature curve between the two extremes shown in Figure 2 to approximate the IV curve followed by an SEU current pulse being far from thermal equilibrium In the author s opinion the most relevant way to plot these intermediate I V curves is to artificially increase the thermal conductivity of the substrate material This results in a temperature rise with conduction current that does not occur if the method of using different constant temperature simulations are used as in the case for some of the simulations shown in reference 1 Another method to produce a non equilibrium I V curve would be to use a voltage time transient simulation but this method suffers from the complication that another variable has to be accounted for namely the avalanche multiplication time which can result in serious voltage overshoot as the avalanche multiplication process builds up The voltage overshoot also depends on the chosen ramp rate Using this new method of increasing the thermal conductivity to emulate transient heating effects a number of simulations were run multiplying the thermal conductivity by x10 x100 x1 000 x10 000 and x100 000 These additional curves are added to the original curves shown in Figure 2 and are now plotted in Figure 4 Figure 4 I V curves using increasing thermal conductivity to emulate non thermal equilibrium effects from an SEU strike From Figure 4 several effects are apparent From the original constant 300K temperature red curve it seemed that Single Event Burnout SEB could not occur for reverse applied voltages of less than approximately 2 400 volts However as can be seen from Figure 4 the longer the SEU transient current lasts and therefore the hotter the local temperature gets the lower this critical reverse applied voltage becomes where SEB can occur In addition to a lower critical voltage the hotter the local temperature becomes the lower the current required before the secondary high current stable on condition is reached It will be shown later that the yellow curve representing the thermal conductivity increased by 10 000 times is a reasonable approximation to the real transitory curves Further simulations showed that the appropriate value of thermal conductivity multiplier for this particular PiN diode was between 4 500 and 5 000 Figure 5 shows D C simulations using a thermal conductivity 4 500 times the equilibrium value with cathode current plotted on a linear scale between zero to 0 25 Amps versus reverse applied voltage It will be shown later that the cathode current range between zero and 0 25 Amps represents the same range of currents induced by the Single Event Upset in this study with a Linear Energy Transfer values of up to 128 MeV cm2 mg On this curve by converting the cathode current on the vertical axis to equivalent LET value you can directly read off the LET required to trigger a single event burnout event for any given reverse bias on the PiN diode Clearly the reverse bias cannot exceed the 3 500 volt breakdown voltage so bias voltages shown in Figure 5 above 3 500 volts are not meaningful In this curve the initial breakdown currents at 3 500 volts are simply disguised by the linear scale on the Y axis Figure 5 Showing the relationship between LET required induced current to induce an SEB event and applied reverse bias This

Original URL path: http://www.silvaco.fr/tech_lib_TCAD/simulationstandard/2014/jul_aug_sep/a1/a1.html (2016-05-03)

Open archived version from archive - High Voltage Power Device Modeling with HiSIM_HV 2

effects will be explained first followed by a step by step description of model parameter extraction using Utmost IV Finally depletion mode which is implemented in the latest version of HiSIM HV 2 2 0 will be introduced What attendees will learn Device structures and the electrical characteristics MOS LDMOS HVMOS Extended Drain MOS XDMOS Release history of HiSIM HV models HiSIM HV 1 2 0 2 1 0 and 2 2 0 HiSIM HV 2 model review HiSIM 2 core and the quasi 2 D resistor model HiSIM HV 2 model extraction flow New depletion mode in HiSIM HV 2 2 0 Presenter Yoshihisa Iino is a Staff Engineer at Silvaco Japan and has been employed at the company for 20 years Since then he has been in charge of the Utmost device characterization and SPICE modeling product Prior to joining Silvaco Japan he worked at a bipolar IC company and was tasked with establishing a CMOS technology development platform which included the use of Silvaco tools Prior to this he worked at Texas Instruments Japan Limited where he was a principal characterization engineer for the extended drain MOS device technology and was responsible for defining process conditions and

Original URL path: http://www.silvaco.fr/webinar/high_voltage_power_device_modeling_with_hisim_hv2.html (2016-05-03)

Open archived version from archive - TCAD to SPICE Simulation of SiC and Si Power Devices Webinar - Archive

SiC have begun to attract attention due to their projected improved performance over silicon Simulating SiC devices is more challenging relative to silicon based devices In this webinar we will review the requirements to accurately simulate SiC based power devices We will also present a completely automated TCAD to SPICE flow that helps reduce the cost and time taken to develop a Silicon based IGBT power device What attendees will learn Key challenges of power device TCAD simulation Key challenges of SiC TCAD simulation TCAD simulation of SiC IGBT Trench MOS and DMOS 2D and 3D TCAD simulations meshing solver physical models When to use 3D over 2D Full TCAD to SPICE IGBT flow example Process and Device simulations for IV curve generation TCAD based SPICE parameter extraction using HiSIM IGBT compact model Correlation between circuit performance and process variation Circuit performance optimization Presenter Dr Eric Guichard is Vice President of the TCAD Division He is responsible for all aspects of the TCAD division from R D to field operations Since joining Silvaco in 1995 he has held numerous positions including director of Silvaco France and most recently Director of Worldwide TCAD Field Operations Prior to joining Silvaco Dr Guichard

Original URL path: http://www.silvaco.fr/webinar/tcad_to_spice_simulation_of_sic_and_si_power_devices.html (2016-05-03)

Open archived version from archive - Atlas Simulation of GaN-Based Super Heterojunction Field Effect Transistors Using the Polarization Junction Concept

their work function identical to the electron affinity of the AlGaN layer The gate forms a Schottky contact to the AlGaN layer The base electrode makes an ohmic contact to the 2DHG through the top p GaN layer and is electrically connected to the gate by specifying COMMON parameter on the CONTACT statement Figure 1 Cross sectional diagram of a GaN Super HFET left and interface charge density under the base electrode right Atlas uses specific physical models and material parameters to take into account the mole fraction and doping of the AlGaN GaN system 3 We chose to model low field mobility using the ALBRCT model allowing the separate control of electrons and holes We selected a nitride specific high field mobility model by specifying GANSAT N on the MODEL statement In order to take into account the relatively deep ionization levels for acceptors in p type GaN we set the INCOMPLETE parameter on the MODEL statement 4 In the simulation of high current operation self heating effect may be important We set the LAT TEMP parameter on the MODEL statement to enable the heat flow simulation by the GIGA module As for the breakdown simulation an impact ionization model should be taken into account We can use the tabular Selberherr model with the build in parameters for GaN Performance of GaN device and convergence of its simulation can be significantly influenced by the presence of defects We introduced bulk and interface traps by setting DOPING and INTTRAP statements in this Super HFET simulation Threshold voltage and substrate leakage current are controlled by a concentration of acceptor and donor traps in the GaN buffer layer respectively Moreover we put the interface traps to represent Fermi level pinning at the bottom of the GaN buffer This assumption is properly valid because an actual GaN epitaxial layer has quite many defects around the interface with the substrate It should be noticed that these traps play an important role in the convergence of the device simulation including a floating undoped GaN buffer region Simulation Results and Discussions Figure 2 shows the band diagram and the vertical carrier profile under base electrode calculated at zero bias condition As reported in 2 the accumulation of 2DEG and 2DHG has been verified at the lower and upper heterointerfaces respectively Figure 2 Band diagram left and vertical carrier profile right under the base electrode The simulation results of the Id Vg and Id Vd characteristics are shown in Figure 3 and Figure 4 respectively Very good agreement between simulations and experiments were obtained by setting some parameters properly For example the donor trap density in the GaN buffer determines the substrate leakage current and the acceptor trap density in GaN buffer affects the threshold voltage and the maximum drain current The ALPHA parameter on the THERMCONTACT statement has an impact on the negative differential resistance at high current operation as well as the maximum drain current Figure 3 Simulated Id Vg characteristics of the GaN Super

Original URL path: http://www.silvaco.fr/tech_lib_TCAD/simulationstandard/2014/jan_feb_mar/a2/a2.html (2016-05-03)

Open archived version from archive - Simulating the Effects of Stress/Strain on a 50 nm Silicon FinFET

100 nm Si 3 N 4 capping layer was deposited on top of the structure We adjusted the mesh spacing to 5 nm in the active region of the device and made it progressively coarser elsewhere The final structure is shown in Fig 1 Figure 1 The FinFET structure generated by VICTORY CELL The Si 3 N 4 layer is shown transparent in order to display the Silicon Fin and Polysilicon Gate underneath 3 VICTORY STRESS The structure created by VICTORY CELL was imported into VICTORY STRESS which was used to perform a stress analysis over the whole FinFET device structure The Si 3 N 4 capping layer see Fig 1 was set to have uniform hydrostatic tensile stress of 1 GPa The bottom left and right surfaces of the FinFET were constrained at zero displacement Stress analysis was performed for a fin oriented along 100 direction on the wafer 100 surface i e in this particular work FinFET orientation is 100 100 Fig 2 shows the XX component of the strain tensor in a cut plane along the center of the device Figure 2 The XX strain in a cut plane along the center of the device VICTORY STRESS accounts for all isotropic and anisotropic properties of the materials boundaries and initial conditions The evaluation of mobility enhancement factors along the fin is based on a full 3D piezoresistive model Stress effects repopulate the electron conduction bands resulting in the observed change in effective mobilities The relative mobility enhancement along the fin XX tensor component is shown in Fig 3 The center of the active region Fig 3 inset shows a mobility enhancement of up to 100 Figure 3 The Mobility Enhancement in the XX direction along the axis of the silicon fin Insert The XX Mobility Enhancement in a cut plane through the active region 4 VICTORY DEVICE The structure along with the stress strain and mobility enhancement data was then loaded into VICTORY DEVICE for electrical simulation and analysis Source and drain electrodes were defined at either end of the Silicon fin the Polysilicon region was defined to be the gate and we put a substrate contact at the bottom of the device We also set the workfunction of the gate to 4 17 eV Aside from the standard silicon models cvt consrh etc we used the strain dependent mobility enhancement models nhance and phance for this simulation The mobility enhancement models apply the second order mobility enhancement tensor calculated by VICTORY STRESS see Fig 3 directly to the low field mobility This results in directionally dependent anisotropic electron and hole mobilities To get an idea of the cut off behavior of the device we first performed a sweep of the gate voltage from 0 to 3 Volts The results show a significant increase in drain current when strain is considered in the calculation see Fig 4 Figure 4 The drain current of the FinFET at Vdrain 0 1V for gate Voltages ranging from 0 to 3V

Original URL path: http://www.silvaco.fr/tech_lib_TCAD/simulationstandard/2009/oct_nov_dec/a1/a1.html (2016-05-03)

Open archived version from archive