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  • SILVACO TCAD Knowledge Base - Recommended Textbooks
    the VLSI Era Vol 2 Process Integration Stanley Wolf c 1990 752pp ISBN 0 9616721 4 5 Silicon Processing fo rthe VLSI Era Vol 3 The Submicron MOSFET Stanley Wolf c 2002 726pp ISBN 0 9616721 5 3 Silicon Processing for the VLSI Era Vol 4 Deep Submicron Process Technology Stanley Wolf c 2002 826pp ISBN 0 9616721 7 X Silicon VLSI Technology James D Plummer Michael D Deal Peter

    Original URL path: http://www.silvaco.fr/tech_lib_TCAD/whitePapers/recommendedTextbooks.html (2016-05-03)
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  • SILVACO Presentation Materials
    Mixed Signal Circuit Simulation Harmony SPICE Model Extraction Utmost III Utmost IV Spayn CORPORATE About Us News Management Partners Careers Conferences Goverment Programs Locations Contact Us Solutions Overview Display Power Reliability Optical Advanced Process Development Analog HSIO Design Library Memory

    Original URL path: http://www.silvaco.fr/tech_lib_EDA/kbase/AMS/index.html (2016-05-03)
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  • Analog / Mixed Signal / RF - Application Notes
    Circuit Design Using Local and Global Optimization 1 021 Get the Best Performance From Your Verilog A Model 1 020 Debugging Verilog A Flow Under Windows 1 019 EDIF 2 0 0 Conversion Guidelines for Importing Legacy EDIF Files for First time Users 1 018 HiSIM HV Single Geometry Parameter Extraction with Automated Utmost IV Optimization 1 017 Interactive Measurement in SmartView 1 016 HiSIM HV Local Optimization Templates Prepared for Utmost III 1 015 Performing Operation Point Analyses with Variable Sweeps 1 013 Creating Netlists for Harmony Mixed Signal Simulations 1 012 Importing Standard design Libraries using EDIF 2 0 0 1 011 Know More About Verilog A Parser in SmartSpice 1 010 Simulating Circuits with Parasitics and RCL Reduction 1 009 Phase Noise Simulation with SmartSpice RF 1 008 Schematic Driven Process Corners Analysis 1 007 Spiral Inductors PDK Flow Using Quest Utmost IV SmartSpice and Spayn 1 006 Guide To Utmost IV Optimizers 1 005 Transceiver Block Simulation with SmartSpice RF 1 004 Using Verilog A to Simplify a Netlist 1 003 SmartSpice SEU Module 1 002 Physical 3D Single Event Upset Simulation of a SRAM Cell with Victory and SmartSpice SEE 1 001 Salvaging Old Designs

    Original URL path: http://www.silvaco.fr/tech_lib_EDA/appNotes/AMS.html (2016-05-03)
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  • Analog / Mixed Signal / RF - White Papers
    More About Analog Mixed Signal RF Publications Presentation Materials Application Notes Training Materials Published Papers Recommended Textbooks Examples CORPORATE About Us News Management Partners Careers Conferences Goverment Programs Locations Contact Us Solutions Overview Display Power Reliability Optical Advanced Process Development

    Original URL path: http://www.silvaco.fr/tech_lib_EDA/white_papers/index.html (2016-05-03)
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  • Training Materials - Analog / Mixed-Signal / RF
    Modules Part 1 Getting Started 1 2Mb pdf Part 2 SmartView 288k pdf Part 3 SmartSpice Convergence Tips 316k pdf Part 4 SmartSpice Optimizer 452k pdf Part 5 SmartSpice Verilog A 416k pdf Part 6 SmartSpice Lab Instructions 354k pdf Examples 12k Zip file CORPORATE About Us News Management Partners Careers Conferences Goverment Programs Locations Contact Us Solutions Overview Display Power Reliability Optical Advanced Process Development Analog HSIO Design Library

    Original URL path: http://www.silvaco.fr/tech_lib_EDA/trainingMaterials/AMS.html (2016-05-03)
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  • Published Papers - Analog / Mixed-Signal / RF
    Fast Slow models and Statistical models Proc SISPAD 1998 pp 85 88 M A Imam M A Osman and A A Osman MOSFET global modeling for deep submicron devices with a modified BSIM1 SPICE model IEEE Trans Computer Aided Design Vol 15 Apr 1996 pp 446 451 R Clancy M Welten J A Power B Mason P Stribley and A Mathewson A comparison of RS 1 and SPAYN for the generation of worst case SPICE level 3 MOSFET model parameters IEE Colloquium on Improving the Efficiency of IC Manufacturing Technology 1995 pp 7 1 7 4 M Welten et al Enhanced Worst Case Simulation Utilising Regression based performance spread Proc ESSDERC 95 The Hague Netherlands pp 761 764 J Power et al Relating Statistical MOSFET Model Parameter Variabilities to IC Manufacturing Process Fluctuations Enabling Realistic Worst Case Design IEEE Trans on Semiconductor manufacturing Vol 7 August 1994 pp 306 318 Clancy Welton Wall Power Mason Stribley Mathewson Statistical Worst Case Analysis Techniques for CMOS Technology Using Design of Experiments K Burke et al Worst Case MOSFET Parameter Extraction for a 2um CMOS Process Proc IEEE 1994 ICMTS Vol 7 pp 119 125 Power Donnellan Burke Moloney Mathewson Lane Generation of MOS Model Parameters Covering Statistical Process Variations ESSDERC 1993 Power Mathewson Lane An Approach for Relating Model Parameter Variabilities to Process Fluctuations IEEE ICMTS 1993 Power Barry Mathewson Lane Accurate and Efficient Predictions of Statistical Circuit Performance Spreads IEEE CICC 1992 Power Lane An Enhanced SPICE MOSFET Model Suitable for Analog Applications IEEE Trans CAD 1992 Power Clancy Wall Mathewson Lane An Investigation of MOSFET Statistical and Temperature Effects IEEE ICMTS 1992 Power Mathewson Lane MOSFET Statistical Parameter Extraction Using Multivariate Statistics IEEE ICMTS 1991 Power Barry Mathewson Lane Worst Case Simulation Using Principal Component Analysis Techniques An Investigation ESSDERC 1991 Lin Kuh Marek Sadowska Stepwise Equivalent Conductance Circuit Simulation Technique UC Berkeley CA Lin Mark Sadowska Kuh SWEC A StepWise Equivalent Conductance Timing Simulator for CMOS VLSI UC Berkeley CA Power Lane Enhanced SPICE MOSFET Model for Analog Applications IEEE ICMTS 1990 Moon Hyo Kang Ji Ho Hur Youn Duck Nam Eun Ho Lee Se Hwan Kim and Jin Jang An optical feedback compensation circuit with a Si H thin film transistors for active matrix organic light emitting diodes Journal of Non Crystalline Solids In Press Corrected Proof Available online 5 February 2008 Ryosuke Inagaki Norio Sadachika Dondee Navarro Mitiko Miura Mattausch Yasuaki Inoue A Gate Current Model for Advanced MOSFET Technologies Implemented into HiSIM2 IEEJ Transactions on Electrical and Electronic Engineering Vol 3 Issue 1 Jan 2008 pp 64 71 Y Iino I Pesic HiSIM Replacement of BSIM4 in UDSM circuit simulations 2007 NSTI Nanotechnology Conference and Trade Show NSTI Nanotech 2007 Technical Proceedings Vol 3 2007 NSTI Nanotechnology Conference and Trade Show NSTI Nanotech 2007 Technical Proceedings 2007 pp 682 683 Y S Yu A multi gate single electron transistor model for circuit simulations by SPICE Journal of the Korean Physical Society Vol 50 No 3 March

    Original URL path: http://www.silvaco.fr/tech_lib_EDA/publishedPapers/AMS.html (2016-05-03)
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  • AMS - Recommended Textbooks
    Signal Circuit Design Second Edition R Jacob Baker Published Wiley IEEE Press 2nd Edition Published 2009 pp 330 ISBN 978 0 470 29026 2 Modeling the Bipolar Transistor Ian E Getreu Available via www lulu com iangetreu The Physics and Modeling of MOSFETs Surface Potential Model HiSIM Mitiko Miura Mattauch et al Published 2008 pp 350 ISBN 13 978 981 256 864 9 ISBN 10 981 256 864 6 The

    Original URL path: http://www.silvaco.fr/tech_lib_EDA/kbase/AMS/recommendedTextbooks.html (2016-05-03)
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  • Presentation Materials - Custom IC CAD
    Layout Verification Guardian Full Chip Extraction Hipex CORPORATE About Us News Management Partners Careers Conferences Goverment Programs Locations Contact Us Solutions Overview Display Power Reliability Optical Advanced Process Development Analog HSIO Design Library Memory Design Technical Library Publications Webinars University

    Original URL path: http://www.silvaco.fr/tech_lib_EDA/kbase/customICCAD/index.html (2016-05-03)
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