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  • SILVACO - Custom IC CAD Application Notes
    DRC Error Database to Analyze LVL Run Results 2 010 Parasitic Back Annotation for Post Layout Simulation 2 009 Creating LISA Scripts to Automate Layout Operations in Expert 2 008 Customizing Expert with New Functions Using LISA 2 007 Preserving Parametrized Cells When Translating Competitors Layout Database into Expert 2 006 Central Hipex Database and Improved Hipex C and Hipex R Technology Files 2 005 Selective RC extraction Methods in

    Original URL path: http://www.silvaco.fr/tech_lib_EDA/appNotes/customICCAD.html (2016-05-03)
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  • Published Papers - Custom IC CAD
    of these papers may be found at the IEEE website at www ieee org G Vakanas S Munir E Tejnil D Bald R Nagpal Lithography based automation in the Design of Program Defect Masks Proc SPIE Feb 2004 CORPORATE About Us News Management Partners Careers Conferences Goverment Programs Locations Contact Us Solutions Overview Display Power Reliability Optical Advanced Process Development Analog HSIO Design Library Memory Design Technical Library Publications Webinars

    Original URL path: http://www.silvaco.fr/tech_lib_EDA/publishedPapers/customICCAD.html (2016-05-03)
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  • SILVACO Presentation Materials Structure Characterization
    Characterization Cell Level Extraction CORPORATE About Us News Management Partners Careers Conferences Goverment Programs Locations Contact Us Solutions Overview Display Power Reliability Optical Advanced Process Development Analog HSIO Design Library Memory Design Technical Library Publications Webinars University Program Overview Partners

    Original URL path: http://www.silvaco.fr/tech_lib_EDA/kbase/interconnect/index.html (2016-05-03)
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  • Training Materials - Interconnect
    Frequency Parasitic Extraction 4 81Mb pdf CORPORATE About Us News Management Partners Careers Conferences Goverment Programs Locations Contact Us Solutions Overview Display Power Reliability Optical Advanced Process Development Analog HSIO Design Library Memory Design Technical Library Publications Webinars University Program

    Original URL path: http://www.silvaco.fr/tech_lib_EDA/trainingMaterials/parasiticExtraction.html (2016-05-03)
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  • Published Papers - Interconnect
    of Cu local interconnect on LSI performance Materials Transactions Vol 43 Jul 2002 pp 1574 1576 Bermond C et al Characterization of dual damascene Cu SiO sub 2 interconnects in time and frequency domains Advanced Metallization Conference 2000 AMC 2000 pp 19 24 R R Song G Ruan X Xiao R Streiter T Otto and T Gessner Geometrical optimizing design of interconnection for deep sub micrometer VLSI circuits in Chinese Research Progress of Solid State Electronics Vol 20 No 1 2000 pp 84 93 Bermond C Flechet B Le Carval G Charlet F Morand Y Angenieux G Salik R Performance Characterization of Advanced Interconnect on High Speed VLSI Circuits Proc ESSDERC 2000 pp 216 219 B Froment et al Ultra low capacitance measurements in multilevel metallisation CMOS by using a built in Electron meter IEEE J SS Ccts 1999 Chia Fu Chou et al Sorting of biomolecules via microdevices Proc IEDM 1999 B Froment et al New Interconnect capacitance characterization method for multilevel metal CMOS processes Proc IITC 1999 C Bermond et al Performance Characterization of Advanced Interconects on High Speed VLSI Circuits Proc ESSDERC 99 pp 216 219 S Putot et al A Fast and Accurate Computation of Interconnect Capacitance Proc IEDM Tech Dig 1999 pp 893 896 G LeCarval et al Benoit Froment and Herve Jaouen Validation of CLEVER Interconnect Parasitics with 0 18 m Process Measurements SGS Thomson Microelectronics Advanced Interconnect Scheme Analysis Real Impact of Technological Improvements Proc IEDM Tech Dig 1998 pp 837 840 I Kamohara Statistical simulation methodology for multi level interconnect contact analysis and step coverage evaluation In 1997 2nd International Workshop on Statistical Metrology 8 June 1997 Kyoto Japan pp 113 116 R Salik P Ferrari A Chosson and G Angnieux Electrical performance in time domain of subminiature interconnections on new thin

    Original URL path: http://www.silvaco.fr/tech_lib_EDA/publishedPapers/parasticExtraction.html (2016-05-03)
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  • Presentation Materials - Digital CAD
    Cell Core Characterization AccuCell AccuCore Place and Route Spider CORPORATE About Us News Management Partners Careers Conferences Goverment Programs Locations Contact Us Solutions Overview Display Power Reliability Optical Advanced Process Development Analog HSIO Design Library Memory Design Technical Library Publications

    Original URL path: http://www.silvaco.fr/tech_lib_EDA/kbase/logicVerification/index.html (2016-05-03)
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  • SILVACO - Digital CAD Application Notes
    Work Flow and Processing Options 4 008 How to Define Optimal Slopes Loads for Cell Characterization 4 007 Automatic Port Determination in Catalyst 4 006 Characterize I O Cells Using AccuCell 4 005 LINT Your Design with Silos 4 004 Silos Code Coverage 4 003 Using PLI to Implement a User Defined System Task for Use with Silos and Harmony 4 002 Manual Latch Flip Flop Recognition in AccuCell and

    Original URL path: http://www.silvaco.fr/tech_lib_EDA/appNotes/digital.html (2016-05-03)
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  • Training Materials - Digital CAD
    Training Block Characterization Modeling and STA 2 3Mb pdf Product Overview of Block Characterization Modeling and STA 1 26Mb pdf AccuCore Static Timing Analysis Commands and Concepts 1 49Mb pdf SPICE Accurate Core Characterization with STA 1 46Mb pdf Spider Spider Place and Route Training Day 1 9 9Mb pdf More About Digital CAD Publications Presentation Materials Application Notes Training Materials Recommended Textbooks Examples CORPORATE About Us News Management Partners

    Original URL path: http://www.silvaco.fr/tech_lib_EDA/trainingMaterials/digital.html (2016-05-03)
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