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  • SILVACO - Silvaco Delivers TMA-Compatible TCAD Simulators
    based in Switzerland Synopsys announced its future TCAD products would be based on the ISE software Silvaco has been aggressively improving the original Stanford software to meet all the needs of our worldwide customers who develop state of the art technologies said Dr Ivan Pesic CEO of Silvaco Many companies have asked Silvaco to deliver TMA compatibility we obliged Silvaco will continue to provide advanced TCAD technologies based on the latest physical models for process and device simulation Silvaco is the only company dedicated to exclusively support the Stanford TCAD legacy Switching to Silvaco TCAD means that TMA customers do not have to recalibrate their model coefficients re establish their process and device simulation flows developed over many years and learn new software About Silvaco TCAD Tools ATHENA Process Simulation Framework enables process and integration engineers to develop and optimize semiconductor manufacturing processes ATHENA provides an easy to use modular and extensible platform for simulating ion implantation diffusion etching deposition lithography oxidation and silicidation of semiconductor materials It replaces costly wafer experiments with simulations to deliver shorter development cycles and higher yields ATLAS Device Simulation Framework enables device technology engineers to simulate the electrical optical and thermal behavior of semiconductor

    Original URL path: http://www.silvaco.fr/news/pressreleases/2005_07_27_01.html (2016-05-03)
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  • SILVACO - Silvaco Releases Stand-alone Proprietary Encryption Program
    providers FPGA manufacturers and IP companies can securely distribute encrypted circuit blocks containing important intellectual property IP to their customers This technology also enables foundries to encrypt SPICE model libraries for distribution to their customers is a secure manner The de encryption algorithms are built into SmartSpice and other Silvaco software products as a standard feature at no additional cost Our foundry partners were the first to request this standalone encryption technology to distribute their model libraries said Dr Ivan Pesic president and CEO of Silvaco And ever since we introduced IBIS modeling in SmartSpice our PCB design customers FPGA vendors and IP vendor customers echoed the same request for standalone encryption to protect their valuable intellectual property The Silvaco encryption technology uses a secure and robust encryption engine that encodes device model libraries subcircuits and all other input files up to and including a complete SmartSpice input deck Encrypted model and circuit libraries are treated as black boxes providing users with access only to terminal functions Users cannot view or print the encrypted netlists internal node voltages or model parameters The simulation process flow is exactly the same as without encryption so that users do not have to change

    Original URL path: http://www.silvaco.fr/news/pressreleases/2005_08_08_01.html (2016-05-03)
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  • SILVACO - Silvaco Delivers MOSIS SCMOS Process Design Kit
    IC design capture simulation layout and verification tools Silvaco design tools and this PDK provide a solid platform for our customers to take advantage of our low cost prototyping services to design ICs targeting any of our supported processes said Cesar Pina director of MOSIS This multi foundry lambda based process design kit complements our support for vendor rule specific designs Silvaco s PDK based IC design flow has met the challenge of building a flexible multi process kit for educational applications and low volume commercial designs said Kenneth Brock vice president of marketing for Silvaco Our integrated Linux Solaris and PC based tools enable our PDK development team to rapidly deliver foundry specific analog mixed signal RF PDKs for high volume designs Availability The MOSIS SCMOS SCMOS SUBM and SCMOS DEEP PDK is available for download from Silvaco s website at no cost Silvaco s analog mixed signal RF design tools are now available on Windows Linux and Sun Perpetual time based and site licenses are available for workgroup configurations of these products For further information on these products please contact sales silvaco com Universities can receive significant discounts for classroom packages through academicsales silvaco com About MOSIS MOSIS is a low cost prototyping and small volume production service for custom ICs Since 1981 MOSIS has fabricated more than 50 000 integrated circuit designs for commercial firms government agencies and universities MOSIS provides designers with a single interface to the constantly changing technologies of the semiconductor industry Mask generation wafer fabrication and device packaging are contracted to leading industry vendors The cost of fabricating prototype quantities is kept low by aggregating multiple designs onto one mask set This allows customers to share overhead costs associated with mask making wafer fabrication and assembly MOSIS gives access to a wide variety

    Original URL path: http://www.silvaco.fr/news/pressreleases/2005_08_11_01.html (2016-05-03)
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  • SILVACO - IEDM
    Monday December 13 2004 9am 9pm Tuesday December 14 2004 9am 9pm Wednesday December 15 2004 9am to 12pm See demonstrations of current and future TCAD and Parasitic extraction software meet our TCAD experts and hear about our new OMNI licensing methodology that gives you instant access to the broadest selection of leading edge TCAD IC CAD and AMS simulation software tools for commercial design research and teaching Our new

    Original URL path: http://www.silvaco.fr/news/pressreleases/2004_12_09_04.html (2016-05-03)
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  • SILVACO - News - Silvaco Delivers Complete IC CAD Tool Flow on Linux and Solaris
    of marketing at Silvaco Silvaco s integrated custom IC design platform now offers a feature rich set of tools with full cross platform capability with screaming performance Silvaco has been redesigning its tools to take advantage of this modern GUI and inter tool communication for over a year to achieve several critical objectives in response to customer demands All tools must have same look and feel Increased interactive performance Seamless inter tool communication for schematic driven layout and back annotation User customizable interface including configurable tool bars and dock able windows Free cross platform license migration for Gateway Expert and Guardian Complement existing products already ported to Qt including SmartSpice Circuit Simulator and the HIPEX Parasitic Extraction Tools Silvaco s custom IC design platform offers a compelling alternative to high priced custom IC design tools and low cost partial solutions that do not offer integrated schematic circuit simulation layout verification and parasitic extraction solutions Silvaco provides worldwide customer support training process design kit PDK development and SPICE modeling to serve its customers and foundry partners Pricing and Availability Silvaco s IC CAD tools are available now on Windows Linux and Solaris Perpetual time based and site licenses are available for

    Original URL path: http://www.silvaco.fr/news/pressreleases/2004_06_07_03.html (2016-05-03)
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  • SILVACO - News - Silvaco Pioneers Integrated Solution to NanometerSingle Event Effect Failures
    design At the device level a TCAD device simulator analyzes the physics behavior of a device being hit by an SEE At the circuit level a SPICE simulator predicts circuit behavior after an SEE At the cell level characterization tools develop the cell views that digital EDA tools use to synthesize place and route logic cells into blocks At the block or chip level a full chip parasitic extractor determines which signals are susceptible to SEEs based on their node capacitance and resistance Finally a fault simulator determines if an SEE disrupts the logic behavior of the block or chip based on the gate level netlist stimulus response test vectors and capacitance thresholds The SEE problems are similar to nanometer noise coupling issues except the aggressor is a random SEE stated Dr Chris Nicklaw vice president of research and development The integration of TCAD circuit simulation and mixed level fault simulation tools are required to accurately identify model and mitigate SEE issues in nanometer processes ATLAS 2 3D SEE Module ATLAS Device Simulation enables device technology engineers to simulate the electrical optical and thermal behavior of semiconductor devices The SEE Module enables engineers to vary the energy of the particle where it hits the device and the angle of penetration The device s response to SEEs is transferred to SPICE through a compact model or Verilog A SmartSpice Circuit Simulator SEE Module SmartSpice Analog Circuit Simulator delivers the highest performance and accuracy required to design complex analog circuits analyze critical nets characterize cell libraries and verify analog mixed signal designs The SmartSpice SEE module enables semiconductor engineers to build a library of SEE stimulus response models in compact models or in Verilog A HIPEX Full Chip Parasitic Extraction HIPEX Full Chip Parasitic Extraction products perform 3D accurate and 2D fast

    Original URL path: http://www.silvaco.fr/news/pressreleases/2004_06_07_02.html (2016-05-03)
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  • SILVACO - News - Silvaco Launches Harmony-AMS Analog/Mixed-Signal Simulator
    parasitic extraction and back annotation offers a high productivity platform for mixed signal IC design Both Silvaco and Simucad have attempted mixed signal simulation solutions several times since 1992 using different methods rollback master slave lock step to connect event driven simulators and timestep driven simulators These previous attempts as well as other commercial offerings available today were unable to provide the design partitioning synchronization convergence and single viewing environment between testbenches behavioral models gate level models transistor level netlists and parasitic back annotation required by mixed signal design engineers Harmony AMS is the most exciting product that we have ever created here at Silvaco It provides an elegant solution for the complex challenges facing mixed signal designers stated Dr Chris Nicklaw vice president of research and development SmartSpice A Superior Circuit Simulator SmartSpice Analog Circuit Simulator delivers the highest performance and accuracy required to design complex analog circuits analyze critical nets characterize cell libraries and verify analog mixed signal designs SmartSpice is compatible with popular analog design flows and foundry supplied device models SILOS A Veteran Verilog Simulator SILOS Verilog Simulator is an easy to use IEEE 1364 2001 compliant simulator used by thousands of IC designers A time

    Original URL path: http://www.silvaco.fr/news/pressreleases/2004_06_07_01.html (2016-05-03)
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  • SILVACO - News - Silvaco Rolls Out SmartSpice-RF and Inductance Extractor
    engineers require harmonic balance circuit simulation and an effective noise solution to prove their designs said Ken Brock vice president of marketing at Silvaco SmartSpice RF accurately and efficiently simulates noise gain compression harmonic distortion oscillator phase noise and intermodulation products in non linear circuits using SPICE netlists SmartSpice RF harmonic balance simulator provides frequency domain steady state large signal analysis of non linear circuits driven with multi tone sources It performs complete set of periodic and quasi periodic steady state analyses for large signal and small signal applications each with full parametric sweep and Monte Carlo control parameters Applications include amplifiers mixers multipliers oscillators VCOs AGCs PLLs muxs demuxs clocks CDRs and other RF circuits Accurate Wireless Measurements and Optimizer SmartSpice RF measures spectral regrowth ACPR NPR simulations of amplifiers mixers I Q modulator simulations characterization of the transmission link quality of communications systems and other key wireless measurements It includes a powerful parameter optimizer for gain matching networks IP3 and power dissipation for new circuit design or process migration QUEST High Frequency Parasitic Extractor QUEST calculates 3D frequency dependent inductance resistance capacitance and capacitive loss for any multi port network for RF SPICE analysis It creates frequency dependent W element transmission lines multi port S parameters and spiral inductor standard SPICE models directly from GDSII layouts using an interactive GUI interface Complete RF Design Environment SmartSpice RF leverages all SmartSpice models for large signal small signal noise and parameter output It is integrated with Silvaco s complete PDK supported mixed signal RF physical design flow consisting of Gateway Schematic Editor SmartSpice Circuit Simulator Expert Layout Editor Guardian DRC LVS LPE and HIPEX Full Chip Parasitic Extraction It also can be used within other popular EDA flows Pricing and Availability SmartSpice RF and Quest are available now on Linux

    Original URL path: http://www.silvaco.fr/news/pressreleases/2004_06_01_01.html (2016-05-03)
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