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  • Analog HSIO Design
    even more challenging It is almost impossible to design a modern SoC without high speed I O interfaces so this design needs to be efficient since it is typically on the critical path to tapeout High performance analog design including the design of high performance I Os is largely a manual process requiring a top quality layout editor a very accurate extractor and circuit simulation that supports a wide variety of analyses Silvaco s suite of tools provides all of this Layout has a wide range of foundry PDK support It also supports OpenAccess iPDKs for ease of moving designs between different environments Once layout is created the 3D extraction technology can be used for a full 3D field solver to extract the most accurate parasitics including inductance for high sensitivity analog blocks Custom Design Flow and Foundry Partners Silvaco s circuit simulator provides golden SPICE accuracy In particular the models are validated for TSMC s FinFET nodes Simulation supports transient noise analysis and RF analysis For handling extracted netlists which can be very large there is high capacity parallel SPICE capability along with accurate RC reduction algorithms At advanced nodes there is increasing need to verify the power integrity of a design This entails concurrent EM IR Thermal analysis which is available as an extension to Silvaco s SPICE capability InVar SmartSpice Power Integrity Signoff Capabilities 3D Parasitic Extraction for High Sensitivity Analog Blocks 3D Extraction for Inductors Parallel SPICE for high accuracy FastSPICE for Large Extracted Post layout Simulation AMS Simulation Transient Noise Analysis RF Analysis PSS PNOISE Virtuoso Integration TSMC Model Certification for FinFET Nodes Fast Monte Carlo analysis to save simulation runs Local mismatch analysis Statistical corners for quick design iterations High sigma design for medical automotive applications Wide Range of Foundry PDK Support OpenAccess iPDK

    Original URL path: http://www.silvaco.fr/solutions/analog_hsio/analog_hsio_design.html (2016-05-03)
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  • Power
    applications are not the same engineers as design the devices themselves What is required is a link from TCAD to SPICE so that circuit performance can be measured without having to process real wafers which is both expensive and slow Once SPICE models exist then design can proceed much like any analog design with layout being created parasitics extracted and then simulations run to determine the performance Mixed mode simulations involving both TCAD and SPICE are also possible Lather rinse and repeat Another key step is reliability analysis The high voltages involved make electromigration and thermal issues in particular more critical Power circuits are also susceptible to high energy particles single event effects or SEE single event burnout SEB and single event gate rupture SEGR In order to increase TCAD runtime efficiency without compromising simulation accuracy it is possible to refine the mesh along the strike path Mixed mode TCAD SPICE Simulation Silvaco has a complete suite of tools from TCAD up through modeling to get to a PDK Then a complete suite of tools for design and analysis including the EM IR Thermal analysis technologies recently acquired through the Invarian merger Capabilities Silicon SiC GaN Wide Bandgap Simulation physical models Delaunay Meshing 80 128 160 bit precision Parallelized PAM Solver MPI Mixed mode TCAD SPICE Simulation Multi cell Large Structure Simulation IGBT current crowding LOCOS Simulation including Robust Stable 3D Oxidation for Trench Isolation Single Event Burnout SEB Single Event Gate Rupture SEGR Single Event Effects SEE Total Dose Mesh Refinement Along Strike Track HiSIM HV2 3 Models TechModeler fast fitting for organic transistors OLED Parallel SPICE for high accuracy Full chip Power IC Simulation with FastSPICE AMS Simulation Transient Noise Analysis Fast Monte Carlo analysis to save simulation runs Local mismatch analysis Statistical corners for quick design iterations

    Original URL path: http://www.silvaco.fr/solutions/power/power.html (2016-05-03)
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  • Library Memory Design
    Very accurate extraction can be done using a full 3D field solver for both SRAM and standard cells to ensure the most accurate parasitic values Since almost all other parts of the design will be built on this foundation it is critical that precise values are obtained since errors will otherwise propagate Standard cells today require characterization at a very large number of process corners and needs to be automated Characterizing a full standard cell library might take as many as 25 000 simulations Silvaco provides an environment for automated standard cell characterization and SRAM characterization For simulating a full SRAM or other large extracted netlists there is high capacity parallel SPICE There is support for OpenAccess making it easy to interoperate with other design environments for the actual IP or SoC design to be done For FinFET nodes 16nm model validation is also done with foundry partners for SPICE simulation accuracy AccuCore Memory Characterization In a modern process even a high drive buffer can overload a minimum width metal line and so it is very important to have power EM IR and thermal analysis for both block level design and full chip level design Silvaco s reliability analysis is certified by TSMC but can be used with any foundry InVar Power EM IR Thermal Analysis Capabilities 3D Parasitic Extraction for SRAM and Standard Cells Parallel SPICE for high accuracy FastSPICE for Large Extracted Post layout Simulation TSMC Model Certification for FinFET Nodes Distributed Monte Carlo Automated Standard Cell Characterization Automated SRAM Characterization High sigma analysis for bitcell 7ó sense amp array Multiple failure zones Binary bimodal distributions non linear behavior Standard Cell library statistical functional verification Fast Monte Carlo analysis to save simulation runs Local mismatch analysis for ADC Statistical corners for quick design iterations Wide Range of Foundry

    Original URL path: http://www.silvaco.fr/solutions/library_memory/library_memory_design.html (2016-05-03)
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  • Advanced Process Development
    recipe details Silvaco has full pathfinding analysis for modern process architectures such as FinFET and FD SOI along with other novel devices In the memory area there is support for ion enhanced etch an important technology for vertical NAND flash and STT MRAM 3D FinFET Path finding Simulation 3D NAND Flash IECE Etch Simulation Standard BSIM models can be extracted from the TCAD models to form the link between the design of the new process and the tool environments which will be used to create the designs for manufacturing There is a full 3D field solver to extract accurate parasitic data for FinFET SRAMs and other novel structures 3D Parasitic Extraction for FinFET SRAM Capabilities Rapid Prototyping and Detailed Physical Simulation Modes FinFET Novel Device Pathfinding Analysis FD SOI Device Pathfinding Analysis Advanced Ion enhanced Etch for 3D NAND Flash and STT MRAM Stress history Laser annealing Epitaxy Diffusion implantation in compound semiconductor Robust Stable 3D Oxidation 3D Parasitic RCX for FinFET SRAMs BSIM CMG BSIMSOI More About Advanced Process Development Simulation Standard Simulating the Effects of Stress Strain on a 50 nm Silicon FinFET Simulation of Ion Beam Etching of Patterned Nanometer scale Magnetic Structures for High Density Storage

    Original URL path: http://www.silvaco.fr/solutions/advanced_cmos/advanced_cmos.html (2016-05-03)
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  • Optical
    technology Silicon Photonics such as edge emitting and VCSEL lasers and waveguides used largely in fiber optic communication systems Silvaco s product suite for CIS goes from TCAD to SPICE modeling and simulation up to custom layout and reliability analysis Building on a foundation of TCAD the process itself can be built up and device analysis and optimization can be achieved TCAD supports ray tracing transfer matrix method simulation TMM finite different time domain simulation for optical simulation CMOS Image Sensor Simulation CMOS Image Sensors are essentially complex analog designs that are a combination of an array of transistors and sense control blocks that have a requirement of extremely high sensitivity Since extracted CIS designs can get very large they require high accuracy and capacity simulation capabilities There are a wide variety of PDKs available from various foundries that have CIS processes Because CISs are typically mounted in some form of 3D packaging running off a battery and are often in physically restricted spaces electromigration IR drop analysis and especially thermal are extremely important and Silvaco s suite of analysis tools can ensure the design of reliable devices CCD solar cells lasers and silicon photonics can be designed using Silvaco s TCAD suite Optical simulation including mode solver and laser whispering gallery mode can be used to simulate the interaction between the silicon and the light that is produced or absorbed Laser and Waveguide Simulation Capabilities Ray Tracing Transfer Matrix Method Simulation Finite Difference Time Domain Simulation Self consistent Helmholtz solver Strain dependent k p Model Mode Solver Laser Whispering Gallery Robust Stable 3D Oxidation for CIS CIS SPICE Simulation Golden SPICE Accuracy Parallel SPICE extended for FastSPICE Applications Large Extracted Post layout Simulation Transient Noise Analysis High sigma analysis for CIS control sense array Fast Monte Carlo analysis to

    Original URL path: http://www.silvaco.fr/solutions/optical/optical.html (2016-05-03)
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  • Display
    that allows the details of the process to be built up The device characteristics that TCAD produces can be used for a first level of analysis and then special SPICE compact models such as RPI for a Si TFT or UOTFT for organic and oxide TFTs can be created A 3D field solver can be used for pixel RC extraction to ensure that the displays have the sensitivity required to meet performance specification Extraction of interconnect RC is also done using a full chip parasitic extractor Because displays are large sometimes very large the simulation capacity is very important A simulator extended to meet FastSPICE applications is available and can run with parallel cores and huge capacity to handle the largest displays Display hysteresis can also be simulated Similarly Silvaco can handle full panel layout of the largest displays with high performance input and output and high performance editing There is a full PDK generation capability to create the links necessary between the TCAD world and the world of design At the design level layout can be created and analyzed again with high capacity so that very large displays can be read written and edited fast Capabilities a Si p Si a IGZO TFT Organic TFT OLED AMOLED AMLCD Lattice Self heating Models Singlet Triplet Exciton Models OLED Transfer Matrix Method Simulation Radiant OLED GUI Finite Difference Time Domain Simulation Pixel RC extraction Interconnect RC extraction for tech file generation LCD static and optical simulation RPI a Si p Si Models UOTFT model organic and oxide TechModeler fast fitting for organic transistors OLED Parallel SPICE for high accuracy sense control circuits Large Capacity for Full Panel FastSPICE Simulation Hysteresis Simulation capability Transmission line S W Fast Database Full Panel Layout Capacity Equal Resistance Router Integrated DRC LVS Full chip Interconnect

    Original URL path: http://www.silvaco.fr/solutions/display/display.html (2016-05-03)
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  • Variability-Aware Design
    upfront is needed The tools need to ensure that designers do not need to be expert statisticians to understand and optimize the impact of process variations on their design Variation Manager Variation Manager is the next generation solution to variation aware design challenges for analog mixed signal and RF designs It proposes a complete suite of variation tools that allow the designer More Library Variation Manager Library Variation Manager is

    Original URL path: http://www.silvaco.fr/products/variation_analysis/variation_analysis.html (2016-05-03)
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  • InVar Power - EM/IR - Thermal
    effects across all process nodes including 20nm and FinFET Silvaco s solution utilizes only industry standard design file formats enabling users to learn the platform in a user friendly environment for quick turn around times Features InVar Power helps designers understand and analyze various effects across design caused by mutual dependency between power and thermal 2D 3D profiles and how dynamic power dissipation affect device behavior in real time InVar EM IR provides comprehensive analysis and retains full visibility of supply networks from top level connectors down to each transistor Unique approach to hierarchical block modeling reduces runtime and memory and keeps accuracy of true flat run Programmable EM rules enable fast technology node switch InVar Thermal scales from single cell design to full chip and provides lab verified accuracy of thermal analysis Feedback from thermal engine to power and EM IR engines provides unprecedented overall accuracy Benefits Lab and foundry verified accuracy Effective prevention of power integrity issues Covers early back end design stages to sign off Broad range of technology nodes covered up to most recent FinFET Analyses do not require complex data preparation or pre characterization Supports electrical and thermal package models Easy learning curve Applications Standard cell designs gate level designs SoC Full chip designs Analog custom designs transistor level designs Analog blocks High speed IO s Custom digital blocks Memories Technical Specifications Analysis Engines for Analog Designs Electrical simulator provides Timing Device models with correct transient thermal parameters provide accurate timing compared to corner based SPICE analysis Power Accurate numbers for every device in SPICE netlist and calculated with effective thermal profile back annotation from InVar Thermal using 2D 3D thermal models InVar s internal engines provide Thermal Accurate calculation of effective transient static temperatures across design based on power input from SPICE engine EM

    Original URL path: http://www.silvaco.fr/products/analog_mixed_signal/inVar/invar.html (2016-05-03)
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