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  • SILVACO - Products - Guardian DRC/LVS/NET Physical Verification
    Guardian performs multiple roles including design rule checks DRC netlist extraction and layout vs schematic LVS comparisons Features Compatible with leading industry DRC tools Supports variety of rule and technology files including Dracula Diva GDSII OASIS Fast intuitive and hierarchical LVS debugging with cross probing to layout and schematic views Netlist extraction supports stress effects and well proximity parameter extraction Tight integration with Expert layout editor allows fast DRC of local area and use of same error database to maintain consistency and integrity Benefits Rule file translators included to import runsets from Dracula and Diva make adoption easy Easy navigation and visualization through graphical and text DRC error reports intuitive for new users and experts Full DRC command set fits every design environment local DRC for interactive usage and full chip DRC in batch mode Connectivity based DRC operations including antenna rule checking Optimized execution of DRC commands using graph based task processing Supports 90 degree 45 degree and all angle objects with no compromise in accuracy critical for analog and mixed signal design layout Hierarchical DRC error reporting maximizes efficiency of layout debugging Multi threading DRC offers dramatic increase in performance and capacity Intuitive hierarchical LVS discrepancy report significantly decreases time for error debugging Direct database links between Gateway schematic editor and Expert layout editor provides cross probing as instant graphical discrepancy reports Black box options for subcircuits provides for incremental LVS comparison in hierarchical mode and easy inclusion of IP blocks into verified design at top level Accurate calculation of geometry dependent SPICE parameters important for analog design with default or user defined equations Precise identification of generic devices e g transistors diodes resistors capacitors user defined devices and or black box sub circuits during LVS trace Efficient full chip layout netlist extraction for semiconductor processes with unmatched

    Original URL path: http://www.silvaco.fr/products/custom_ic_cad/drc_lvs_net_physical_verification/guardian.html (2016-05-03)
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  • SILVACO - Products - Clarity RLC
    value less than a user specified threshold Performs parallel and series merging Performs the netlist reduction in linear time using Scattering Parameter Based Macromodeling method and switches between it and Time Domain Method depending on reduction index of netlist Analyses the interconnect models other than RC trees and therefore coupling capacitors and resistor loops can be handled without loss of generality Supports SPICE DSPF or SPEF formats Silvaco s strong encryption is available to protect valuable customer and third party intellectual property Reduction Productivity Easy to Adopt and Use Preserves the accuracy with less than 3 error compared to SPICE simulations for original networks Reduces up to 95 parasitic elements of RLC network Custom scripts using Lisa Scripting Language for processing of selecting subcircuits cells and nets Comprehensive report about reduction process Available on Linux 64 bit and Windows platforms SmartSpice Simulation RC tree network with 80 000 elements before and after reduction Clarity RLC Inputs Outputs Rev 042413 04 More About Clarity RLC Brochure 1 9 MB Supported Platforms X Supported Platforms 2015 Baseline Enterprise 5 6 and 7 64 bit Windows 7 Professional 64 bit Windows 8 Professional 64 bit Windows 8 1 Professional 64 bit More details

    Original URL path: http://www.silvaco.fr/products/custom_ic_cad/rlc_netlist_reduction/clarity_rlc.html (2016-05-03)
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  • Expert, Layout Editor and Viewer
    errors while editing Supports derived layers Strongly integrated with Guardian DRC and LVS Hipex and Clever Integrated with Calibre Interactive Equal resistance router iPDK support Benefits Enables designers to be more productive when editing larger and more complex designs Intuitive editing and capabilities further enhance designer experience and productivity Allows quick loading of GDSII databases in excess of 10GB in minutes as opposed to traditional hours for reduced time Tight integration with Gateway schematic editor to allow cross probing between logic and physical designs Customizable hotkeys macros and toolbars to emulate look and feel of Virtuoso environment for layout designers Check in check out library manager enables designers to simultaneously work on same project across network Autoscaling and resize feature minimizes process migration efforts Wires and devices at 90 degrees 45 degrees or any angle Any angle rulers for accurate measurement Extensive custom set of PDKs plus support for iPDK Equal resistance router to provide gains in productivity for TFT and Flat panel designers Technical Specifications Various scripting capabilities are supported for more advanced applications including C API for design automation Integration with Calibre Interactive and Calibre RVE using industry standard formats Imports legacy designs with GDSII and CIF data

    Original URL path: http://www.silvaco.fr/products/custom_ic_cad/layout_editing/expert.html (2016-05-03)
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  • Hipex - Full-Chip Parasitic Extraction
    the most suitable extraction mode for design Various netlist formats for parasitic information can be extracted from Hipex including parasitic SPICE back annotated netlists SPICE DSPF SPEF and CSV formats Due to tight integration with the layout editor Expert back annotation is automated to enable accurate post layout simulation and analysis Non shielded lateral multilateral capacitance model Corner capacitance model Custom CPX OVERLAP command for more accurate parasitic capacitance calculation Field solver mode added to allow for accurate parasitic resistance calculation and addition of 3 layer configurations and regions with numerous contacts New output CSV format of extracted parasitic RC netlist allowing to obtain total per net capacitance and point to point resistance Benefits Device extraction support for custom technologies LCD analog mixed and industry standard PDKs Extraction available for MOSFET MESFET BJT JFET diode capacitor resistor and parameterized user defined devices Accurate device extraction for non 45 and non 90 degrees devices Supports black boxing for integration with routing tools Extracts parasitic coupling capacitors for full chip and selected nets Offers user defined or built in capacitance models Supports external capacitance rule files generated by Exact for 3D accurate mode Creates incremental capacitance database on net by net basis Extracts selected nets for fast parasitic C computation of critical paths Processes L T cross and bend resistor shapes Accepts user defined scripts for custom computing of resistance Uses contact over sizing and clustering to simplify resistor shapes Extracts netlist with parasitic resistors hierarchically for full chip or selected nodes Creates incremental resistance database on a net by net basis Multiple extraction models and equation solvers are used for arbitrary shape resistors Splits long conducting tracks for more accurate RC distribution Scripting language support for custom rules Technical Specifications Uses PI model for RC network Striping algorithm and stripe database

    Original URL path: http://www.silvaco.fr/products/custom_ic_cad/full_chip_parasitic_extraction/hipex.html (2016-05-03)
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  • PDKs for Analog/Mixed-Signal/RF Design Houses
    entry to tapeout Silvaco is committed to supporting PDKs for Silvaco EDA tools providing a solution to users Silvaco offers PDKs for most of fab processes of major foundry companies Silvaco PDKs and EDA tools together make chip design easy fast and affordable Key Features Instantly productive environment for new design projects Simple and efficient PDK file usage Support for CMOS Bipolar BiCMOS SOI SiGe TFT CCD and other processes Download PDKs from Silvaco s secure web site PDK Data Flow Silvaco PDK Leadership Development and QA through full design flow Dedicated PDK Developers PDK specialist Close communication with fab and users Uniform PDK file folder format for all PDKs Collaboration with EDA tool developers No system setup required just load files from EDA tools Silvaco PDK in Complete Custom IC Design Platform Schematic Design Using PDK Gateway schematic design flow Symbols Models are included in the PDK Layout Design Using PDK Expert layout design flow The PDK includes technology files PCells and rule files PDK easily and smoothly enables schematic driven layout Foundry Partners Because of their quality and ease of use Silvaco PDKs are being adopted worldwide by leading foundries and design houses Rev 021214 33 More About

    Original URL path: http://www.silvaco.fr/design_flows/pdk.html (2016-05-03)
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  • SmartSpice RF Frequency and time domain RF circuit simulator
    circuits SmartSpice RF envelope analysis and digitally modulated sources library allow RF circuit designers to simulate RF circuits used in communication systems effectively Features Supports periodic steady state analysis of single tone excitation using frequency domain Harmonic Balance and time domain Shooting methods Quasi periodic steady state Spectral analysis for multi tone excitation Steady state AC HAC SPAC small signal analysis Steady state transfer functions HTF SPTF for conversion efficiency image and sideband rejection LO feed through and power supply rejection Steady state NET HNET SPNET to compute S parameters of two port circuits exhibiting frequency translation with scattering S impedance Z admittance Y and hybrid H parameters stability factors different gains stability circles etc Steady state noise HNOISE SPNOISE for output noise spectrum of amplifiers mixers and oscillator phase noise Direct periodic steady state oscillator analysis by Harmonic Balance HOSCIL with phase noise extraction Periodic stability analysis PSTB to evaluate the local stability of a time varying feedback circuits Circuit envelope simulation enables spectral re growth I Q parameters ACPR NPR EVM BER simulations of amplifiers mixers and characterization of the transmission line quality of communications systems using time swept harmonic balance method Smith charts eye diagrams spectral plots histograms signal to noise calculations gain and stability circles constellation diagrams etc Circuit and parameter optimizer for gain matching networks IP3 and power dissipation for process migration Low Noise Amplifier Design LNA Benefits SmartSpice RF harmonic balance simulator provides frequency domain steady state large signal analysis of non linear circuits driven with multi tone sources Time domain shooting method engine simulates periodic steady state of highly nonlinear circuits Optimal convergence with a complete set of interactive control parameters spectral Newton continuation and GMRES solvers Integrated with Gateway schematic editor for schematic entry simulation control interface and testbench design May be

    Original URL path: http://www.silvaco.fr/products/analog_mixed_signal/rf_circuit_simulation/smartspice_rf.html (2016-05-03)
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  • Harmony Analog/Mixed-Signal Simulator
    Accellera Verilog AMS 2 3 1 standard provides language synchronization in connect modules for all analog to digital interfaces Powerful intuitive integrated waveform viewer enables display of analog and digital waveforms on same scale Verilog IEEE 1364 2001 compliant simulator with standard programming language interface PLI Benefits Single kernel engine provides unified mixed signal environment enabling greater convergence and accuracy Back annotation of timing information available through support of SDF format Easy to use graphical user interface provides productive environment for novices and experts selected by 7 major Verilog textbooks Comprehensive project manager saves preferences settings directories and options in file for efficient multi project setup Multi window customizable data analyzer controls pan and zoom timing markers using interactive drag drop capture and display for signals and expressions for analog and digital waveforms Interactive environment enables real time access and analysis of all expressions variables modules signals vectors and registers Consistent interactive methods for signal selection setting time scale bus radix status window timing marker bookmark and bus definition Applications Support for SPICE models for traditional technologies Bipolar CMOS and emerging technologies e g TFT SOI HBT SiGe Harmony Analog Mixed Signal Simulator with Integrated AMS Viewer Technical Specifications Verilog

    Original URL path: http://www.silvaco.fr/products/analog_mixed_signal/harmony.html (2016-05-03)
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  • Verilog-A Language - Source, Compiled and Encrypted
    through model code Verilog A and SmartSpice run time environment integration Compact Model Development Verilog A compact models are compiled into binary code for rapid execution Enables easy development of proprietary SPICE models for specific technologies Integrated development and debugging environment accelerates compact model development Enables mixing of SPICE model statements and Verilog A modules in the same SmartSpice netlist Verilog A environment allows development of compiled models for any DC TRAN AC NOISE or TEMP capability Verilog A Key Features SmartSpice Verilog A is within 2x runtime performance of C compiled ADMS models Compatible with all analog features of the Verilog AMS 2 3 1 language specification Implements small signal and noise sources in multiple distributions Gaussian exponential Poisson chi square Student s T and Erlang Executes analog operators including time integral derivative partial derivative transition slew Laplace transform and Z transform SmartSpice can accept any combination of netlist C C and Verilog A for mixed mode execution Verilog A devices can be referenced using the subcircuit X call Verilog A modules can be referenced using the MODEL statement Memory usage and runtime have been significantly reduced by generating a sparse matrix for individual Verilog A modules Support for encrypting or partial encryption of Verilog A source allows distribution of proprietary models without contents disclosure Supports Single Event Upset SEU analysis A digital PLL example showing a design flow using Verilog A Analog Behavioral Modeling Environment Enables analog designers to build executables for designs of phase locked loops VCOs A D D A etc for prototyping purposes before detailed circuit design Allows designers to describe digital components as sub circuits for mixed signal designs such as Sigma Delta converters Powerful graphical post processor allows waveform overlays to speed up mixedsignal debugging Use of SmartSpice Optimizer with Verilog A SmartSpice

    Original URL path: http://www.silvaco.fr/products/analog_mixed_signal/behavioral_modeling/verilog_A.html (2016-05-03)
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