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  • SILVACO - Simulation Standard - 1994
    Philips Level 9 Models in UTMOST Mixed Mode Simulation Using SmartSpice Volume 5 Number 3 November 1994 A Modern Approach to 0 35u Technology Optimization The Silvaco Solution for Technology CAD ATHENA The Complete Process Simulation Environment ATLAS Breaks New Ground in Device Simulation Simulation Standard Issues Archive 2016 2015 2014 2013 2012 2011 2010 2009 2008 2007 2006 2005 2004 2003 2002 2000 1999 1998 1997 1996 1995 1994

    Original URL path: http://www.silvaco.fr/tech_lib_TCAD/simulationstandard/1994/index.html (2016-05-03)
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  • SILVACO - Simulation Standard - 1993
    Using ATHENA and Flash The First Commercial Simulator for Semiconductor Lasers Submicron Si Si Ge CMOS Circuit Potential Determined Using Mixed Mode Device Circuit Simulation Hints Tips Volume 4 Number 3 December 1993 Device Simulation Advances in 1993 Unique Characterization Capabilities of UTMOST Simulation Standard Issues Archive 2016 2015 2014 2013 2012 2011 2010 2009 2008 2007 2006 2005 2004 2003 2002 2000 1999 1998 1997 1996 1995 1994 1993

    Original URL path: http://www.silvaco.fr/tech_lib_TCAD/simulationstandard/1993/index.html (2016-05-03)
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  • SILVACO - Simulation Standard - 1992
    1992 S Pisces 2B Version 5 0 Arrives Lattice Heating Modeled in S Pisces 2B Simulate Advanced Submicron Devices Using the S Pisces 2B Energy Balance and Hydrodynamic Models Volume 3 Number 4 June 1992 Announcing DevEdit Small Signal AC Analysis for CMOS and Bipolar Transistors Simulation Standard Issues Archive 2016 2015 2014 2013 2012 2011 2010 2009 2008 2007 2006 2005 2004 2003 2002 2000 1999 1998 1997 1996

    Original URL path: http://www.silvaco.fr/tech_lib_TCAD/simulationstandard/1992/index.html (2016-05-03)
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  • Spider - Place and Route Design Flow
    external checking GUI and command line interfaces with replay scripting for run time automation Embedded SPICE and RC extraction engines Synthesis Support Automatic synthesis of buffers and inverters to aid timing convergence Integrates with external third party logic and physical synthesis tools through timing driven verilog and DEF based flows Imports verilog netlists SDC SDF timing constraints and Liberty lib timing models LEF DEF physical and technology library and design exchange format support Floorplanning Automatic placement and what if analysis with multiple physical cell types Real time netlist enforced layout and ECO processes assure error free connectivity control with on line independent verification and correction utilities Built in netlist constraint library and database checking and correction utilities assure valid place and route starting conditions and updates Logical hierarchy netlist management with automatic design partitioning and region controlled floorplanning Padframe generation with chip and macro power planning and generation Automatic utilization estimation and aspect ratio control Placement and routing obstruction control features including rectilinear support Displayed weighted flylines during floorplanning allow you to place blocks to correctly minimize congestion Placement Optimization Automatic net length minimization and timing driven algorithms optimize cell placement 2D congestion map of placement Size and or instance controlled clustering Programmable placement strategies permit mixed free form and datapath like cell placement methods Automated CTS Enables Clock Tree CT and High Fanout Net HFN Synthesis Automatically optimizes insertion delay skew and inter clock skew Provides delay transition skew and load net details Routing Performs automatic standard cell and padframe routing Deep Sub Micron DSM design rules support Real time design rule enforced layout and ECO processes assure error free geometry design with on line independent verification and correction utilities Mark specific nets for advanced automatic rip up and re route without needing to completely re run placement and

    Original URL path: http://www.silvaco.fr/products/digital_cad/place_route_design_flow/spider.html (2016-05-03)
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  • Silos - Verilog Simulator
    university VLSI design courses Hierarchy Explorer offers a familiar view of a hierarchical design with drag drop for rapid capture and display of any variables in the design Silos Interactive Environment enables real time access and analysis of all expressions variables modules signals vectors and registers Consistent interactive methods for signal selection setting time scale bus radix status window timing marker bookmark and bus definition Interactive Source Code Editor displays line numbers for stop start and breakpoints Data Tips to view the values of variables and expressions and code coverage information Productivity Interactive Simulation Environment High Performance simulation engine achieves fast simulation results rivaling compiled Verilog for interactive debugging of designs up to several hundred thousand gates with no compile times Interactive interpreted Verilog environment provides a set of multi tasking utilities to edit HDL source set incremental breakpoints stepping or timed simulation real time viewing and error detection Multi window customizable Data Analyzer controls pan and zoom timing markers using interactive drag drop capture and display for signals and expressions for analog and digital waveforms Trace Mode graphically traces all fan in connections to any signal through all levels of circuit hierarchy instantly Watches window displays or forces state values of specified signals and variables while single stepping all set up through drag drop for designer convenience Data Tips in the Source Window display value scope and time of the highlighted expression at the T1 marker in the Data Analyzer Analog waveforms can be displayed in either piecewise linear format or stepping format Lint Capability Checks for more than 500 design rules Checks race conditions and clock domain synchronization Checks for synthesizability and reports potential synthesis and simulation mismatches Optimizes gate usage with detailed reports of inferred registers latches state machines and other sequential elements that will be synthesized

    Original URL path: http://www.silvaco.fr/products/digital_cad/verilog_simulation/silos.html (2016-05-03)
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  • SSuprem4 - 2D Core Process Simulator
    remains inactive due to formation of mixed dopant defect clusters Due to inclusion of a sophisticated Boron Interstitial Cluster BIC model Athena accurately predicts this important effect RTA Diffusion Simulation of 10 seconds boron diffusion at 1000 C after ion implantation at 2 keV with a dose of 1 0 x 10 14 cm 2 Experiment is from B Colombeau s doctoral thesis This type of simulation is extremely difficult because it needs to take into account several competing phenomena including strong defect recombination at the surface and very fast generation and recombination of various pairs and defect clusters Nonetheless advanced diffusion models in Athena show quite good agreement with experimental profiles Oxidation and Silicidation Simulation Various process steps involve surface reactions and material transformations which result in boundary movements volume changes and stress formation SSuprem 4 simulates two of the most important processes oxidation and silicidation Complex local oxidations together with etching and deposition are used to provide advanced isolation structures Silicides are considered as preferred materials for contact and interconnect metallization Deep Trench Isolation The structure above shows trench oxidation with the interstitials injected by oxidation Interstitials injected at the oxidizing interface are trapped in the trench while those in the silicon diffuse around the bottom of the trench and affect diffusion in the areas to the left of the trench Poly Buffered Isolation Shown above is an example of poly buffered LOCOS isolation The lifting of the polysilicon layer due to stress is clearly illustrated Stress in Shallow Trench Structure Stress related reliability and misoperation issues are very important in modern semiconductor technologies The figure demonstrates stresses built near the corners of a shallow trench during oxidation Self Aligned Silicidation SSuprem 4 provides unique capabilities for the simulation of silicide processes It models the two dimensional formation of silicides dopant redistribution and diffusion in the silicide layer The figure above shows the final structure from a self aligned silicidation salicide process Ion Implant Simulation A variety of analytical and Monte Carlo Implant models allow accurate simulation of ion implantation used in all modern semiconductor fabrication technologies Large angle ion implantation is widely used in modern CMOS technology because it allows to optimize 2D junctions by simply varying ion beam direction Predictive simulation of large angle implantation is quite challenging because several important effects have to be taken into account These effects include ion shadowing and backscattering in non planar structure considerable channeling along non vertical crystal channels as well as non trivial effect of surface oxide thickness on probability of ions to scatter into those channels Most of these effects are more pronounced for low energy few keV implants used for shallow junction formation Monte Carlo implantation module accurately takes into account all channeling and topological effects This example shows a 2 keV 10 13 cm 2 P implant at 45 o Aluminium Implants into 6H SiC Monte Carlo simulation of Al implants into 6H SiC at 30 90 195 500 and 1000 keV with doses of

    Original URL path: http://www.silvaco.fr/products/vwf/athena/ss4/ss4_br.html (2016-05-03)
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  • MCImplant - Advanced Monte-Carlo Implantation Simulator
    the 3D simulation of all channeling directions The same implant in a practical structure shows the manifestation of 3D channeling effects under the gate which is enhanced by the presence of a very thin oxide a counter intuitive result MC Implant Features and Models 3D Binary Collision Approximation Monte Carlo simulation technology fully integrated with the Athena process simulation framework MC Implant module is fully multi threaded to take advantage of parallel computing Run time reduction is almost linearly proportional with the number of CPUs Physically based electronic stopping additionally optimized for most widely used ion target combinations Variance reduction technology giving an effective tenfold speedup in simulation time Precise damage accumulation model allows accurate simulation of dose dependent channeling of implants or pre amorphization effects Accurate experimentally verified down to 0 2 keV doping profiles Accurate calculation of de channeling effects caused by damage buildup and previous implant damage surface oxides polysilcon and other materials beamwidth variations implant angle and energy amorphous material in the structure Calibrated electronic stopping for 100 111 and 110 Silicon substrate orientations 3 D Channeling effects included in the generic solution of ion propagation and stopping Multi threaded MC Implant Performance Multi core computers significantly improve run times This figure shows speedup achieved on 16 CPUs computer Quad Core AMD Opterontm Processor 8356 x 4 The Well Proximity Effect was analyzed in 6 hours and 40 minutes on 1 CPU and less than 27 minutes on 16 CPUs by running one million 300 keV Boron ion trajectories MC Implant Materials Support Implantation in any crystal structure for all supported materials in Athena e g diamond Si Ge SiGe moissanite 4H SiC 6H SiC Zincblende GaAs InP 3C SiC Anisotropic electronic stopping essential for the proper simulation of ion implantation in the most complex structures

    Original URL path: http://www.silvaco.fr/products/vwf/athena/mcimplant/mcimplant_br.html (2016-05-03)
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  • Optolith - Advanced 2D Optical Lithography Simulator
    irregular shapes These are test layouts for an LCD application The Optolith interface with MaskViews allows specification of variable transmittance and phase shift In this case the central octagons have 100 transmittance while small regular and irregular spots are of 19 transmittance and 45 degrees phase shifts The two plots show corresponding 2D aerial images calculated by projection imaging module of Optolith insets are 3D views of the central octagonal spot Exposure and Development Simulation in Non Planar Structures Optolith has a great advantage in comparison with other commercial lithography simulators because it can accurately handle non planar structures First of all seamless integration with the SSuprem and Elite modules allows the use of representative non planar substrate geometries Secondly simulation of resist planarization using reflow process gives realistic shapes of resist layer Thirdly the Beam Propagation Method BPM accurately accounts for diffraction and multiple reflection effects in all non planar resist layers with arbitrary shapes Moreover BPM takes into consideration local changes of resist refraction properties with absorbed light energy This example demonstrates these non planar capabilities and particularly the effect of exposure dose on the resist optical properties The figures above show intensity distributions in a non planar structure two upper plots and corresponding developed resist profiles two lower plots The two figures on the left correspond to the case of constant photoresist refraction index The two figures on the right correspond to the photoresist with refraction index varying linearly with the accumulated dose during exposure process The comparison of final structures shows that the dose effect could be very pronounced and should be taken into account The strong reflection from the slopped walls with subsequent undercut during development may even result in complete removal of the resist feature Process Control Smile Plots Complete lithography simulation from imaging to resist development is the only practical methodology of process control One of the key elements of process reproducibility is the depth of focus DOF control Even after resist planariztaion the DOF could be different in various areas of the layout due to topological variations of the preceding process steps In some cases even small changes in DOF or other process parameters may result in unacceptable violations of critical dimensions CDs The main controlling parameter for this CD vs DOF effect is the exposure dose Therefore the only way to characterize the process response is to vary simultaneously defocus and exposure dose and extract corresponding CDs Optolith together with Silvaco Interactive Tools provides an ideal environment for lithography process control The image of Deckbuild in the upper left corner shows a very simple setting for the DBInternal module It consists of the nested loop over dose and defocus parameters of the Optolith template input deck below Deckbuild automatically runs the Optolith simulation 77 times with the defocus parameter varying between 1 and 1 and the exposure dose parameter varying between 100 and 160 All final resist profiles are saved Also the extracted dose exposure matrix of CD values is stored

    Original URL path: http://www.silvaco.fr/products/vwf/athena/optolith/optolith_br.html (2016-05-03)
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