archive-fr.com » FR » S » SILVACO.FR

Total: 337

Choose link from "Titles, links and description words view":

Or switch to "Titles and links view".
  • Elite - Advanced Physical Etching and Deposition Simulator
    and mechanical erosion Multi Level Interconnect Accurate descriptions of multi level interconnect structures can be simulated with Elite The figure shown above illustrates the capability to evaluate the tightly spaced interconnect lines and dielectric film uniformity of complicated interconnect structures The interface with SSuprem4 allows doping and oxidation profiles to be included in the structure Microloading Effect The etch models in Elite take into account both geometrical and advanced physical effects The figure above shows the effect of microloading for Reactive Ion Etching The effective etch rate on the bottom of the trench is smaller for narrower mask windows because the local ion flux is reduced due to shadowing effect Bonded SOI Wafer and Deep Trench Isolation Process This example shows the combination of an Elite and SSuprem 4 simulation of the deep trench isolation process on the Bonded SOI wafer A bipolar power device has been formed in this structure The reflow effect on the surface contact for the power automotive device is also considered Inter metal Dielectric Void Formation Elite can optimize a process to avoid formation of superfluous voids during deposition The example above shows the use of two conductors poly and aluminum that are close together The narrow gap between them can form a void after TEOS deposition as demonstrated in this example The type of inter metal dielectric material thickness of this dielectric method of insulation as well as design rules may affect the integrity of multi level metallization Elite includes a module for evaluating the effects of CMP processes The figure above illustrates the resulting surface evolution during a CMP of a dielectric test structure Such simulations could be used to investigate effects related to pattern density Metal Step Coverage After Reflow This figure illustrates the ability of Elite to model metal step coverage

    Original URL path: http://www.silvaco.fr/products/vwf/athena/elite/elite_br.html (2016-05-03)
    Open archived version from archive


  • MC Etch & Deposit - 2D Monte Carlo Deposition and Etch Simulator
    discs The level of this surface relaxation smoothing is specified by a parameter related to the radius within which the disc can relax This relaxation process simulates limited surface diffusion that usually occurs in the growing layers by reduction of the surface energy associated with areas of high curvature This model therefore allows an estimation of the trends in local film density The figure shows Monte Carlo Ballistic Deposition over step The deposition direction is 45 degrees from the wafer normal The granular structure illustrates a potential void resulting from shadowing effect and variation of density inside the step corner Plasma Etch Model The Plasma Etch Model is based on a Monte Carlo simulation of the ion transport from the neutral plasma through the dark sheath surrounding the electrodes and walls and isolating the plasma The ions are accelerated while traveling through the sheath due to the electrical potential drop between the plasma and electrodes The Monte Carlo simulation follows a large number of ions and considers collisions with other gaseous species present in the etch chamber The simulated Monte Carlo energy angle distribution of ions are used to calculate an ion flux incident on the substrate surface This flux is then used to calculate the etch rate The window of visibility which depends on topology of the surface is taken into account when the local etch rate is calculated The figure shows the effect of the pressure in the plasma reactor chamber on a trench etch in silicon From left to right the pressures used were 10 100 and 1000 mTorrs Monte Carlo Etching Model The Monte Carlo etch model is implemented into Athena Elite The main application of the model is simulation of plasma or ion assisted etching The unique feature of the module is the capability to

    Original URL path: http://www.silvaco.fr/products/vwf/athena/mcdeposit/mcdeposit_br.html (2016-05-03)
    Open archived version from archive

  • S-Pisces - 2D Silicon Device Simulator
    performance DC characteristics such as Gummel plots and I c vs V CE are all easy to simulate Transient calculation of intrinsic switching speeds and f T vs I c are performed using the time domain mode of S Pisces Simulated I C V CE characteristics Simulated Gummel plot I C and I B vs V B and the current gain vs I C Intrinsic switching speed of a bipolar transistor by performing a transient analysis where the base voltage gets pulsed on Characteristics of AC performance to arbitrary high frequencies is possible The figure above shows the cutoff frequency fT as a function of collector current Current gain and other RF figures of merit can also be plotted against frequency A bipolar transistor was simulated in Athena and imported into Atlas Voltages were applied to the collector and base contacts to turn the transistor on The figure illustrates the electron concentration contours and current flow vectors when the device is operating S H Y Z and ABCD parameter analyses are supported The figure above shows a Smith chart with the S11 and S22 parameters plotted on it TonyPlot displays S parameters using Smith charts and polar plots Advanced Device Structures Enhancements to S Pisces enable rapid and robust simulation of SOI transistors Advanced numerical techniques are employed to enable fast calculation of all SOI characteristics including the kink effect The figure above shows the impact ionization rate and current flowlines in a thin layer SOI transistor Above shows the I D V D characteristics of the above device which illustrates both the kink effect and breakdown This is a comparison of electron concentration in the off and on states in a power DMOS device The left hand figure is for the off state with the gate voltage set to zero The right hand figure is with a gate voltage well above threshold The inversion layer can be clearly seen at the surface of the channel As an example of a hybrid device an insulated gate bipolar transistor IGBT is shown here Potential in the on state and current flowlines are shown An equal amount of current density flows between each pair of lines The current flows from the emitter close to the surface under the gate and down into the collector contact on the backside S Pisces includes models to support simulation of EPROMs EEPROMs and FLASH EEPROM cells Hot carrier injection and Fowler Nordheim tunneling are used to charge and discharge the floating gate The figure illustrates potentials and ionization rate in a FLASH EEPROM cell prior to programming The complex geometry is imported automatically from Athena EEPROM device design curves are shown in the three figures above These show programming time vs drain voltage erasing time vs gate oxide thickness and a programming ID VDS curve showing punchthrough High k Dielectrics Mobility reduction for high k materials due to remote Coulomb scattering and remote phonon scattering Breakdown Analysis Breakdown voltages of power devices are improved using multiple

    Original URL path: http://www.silvaco.fr/products/vwf/atlas/spisces/spisces_br.html (2016-05-03)
    Open archived version from archive

  • Blaze - 2D Device Simulator for Advanced Materials
    Vgs values Extraction of device parameters can be performed on these curves Complete HBT Analysis Blaze can simulate HBT devices constructed from several semiconductor layers Blaze self consistently solves complex semiconductor equations to enable detailed optimization of HBT structures Tools within TonyPlot allow easy manipulation of the output data Here the band diagram of the HBT is shown through the intrinsic region Blaze is used to generate Gummel plots for HBTs Additional quantities such as device gain can also be displayed Using DevEdit a nonplanar HBT structure can be created for simulation by Blaze An InGaAs InP HBT structure is illustrated here DevEdit performs automatic meshing for use in Blaze An AC analysis of the HBT provides gain vs frequency plots S parameter extraction and can predict the gain roll off with frequency Impact ionization models allow simulation of breakdown voltages Here BVCEO of the HBT is shown SiGe Technologies In addition to III V based devices Blaze can simulate any compound or elemental semiconductor material Examples of results from a Si SiGe HBT simulation are illustrated below Gain hFE of the SiGe HBT Blaze simulates materials other than III V compound materials such as SiGe This plot shows recombination rate in the base of a SiGe HBT Negative Differential Mobility Negative Differential Mobility Fourier Analysis of Large Signal Response Blaze simulates negative differential mobility as illustrated by the output oscillations of a GaAs Gunn diode A Fourier analysis routine allows the extraction of a frequency spectrum above from any periodic large signal transient simulation output bottom Here the frequency spectrum reveals harmonics in the output of a diode Negative Silicon Carbide and Anisotropic Materials Anisotropic models for mobility permittivity and impact ionization Example of the effects of anisotropic mobility in SiC GaAs MESFET Simulation is used to study the

    Original URL path: http://www.silvaco.fr/products/vwf/atlas/blaze/blaze_br.html (2016-05-03)
    Open archived version from archive

  • MC Device - 2D Monte Carlo Device Simulator
    Includes a bulk simulation mode for modeling charge transport in relaxed and strained silicon in arbitrary directions and under varying fields and stress levels Uses statistical enhancement methods to resolve the tail of the carrier distribution function and analyze hot carrier effects A 40 nm self aligned n MOSFET generated using Athena The average potential and the average vector electric field for Vg Vg 1 V to Vd Vg 1 V The average electron concentration and the average vector velocity direction The average electron energy Transient analysis yields three converging estimates for the steady state drain current for Vg Vd 1 V and Vs Vsub 0 V based on three integrations of the current density from the center left and right of this structure The average distribution function of the source well x 0 4 um channel x 0 0 um drain edge x 0 02 um and drain well x 0 04 um The curves show the heating of electrons as they transverse the channel The diversion of the distribution function from a drifted Maxwellian shows why MC modeling of this device is helpful Rev 110113 04 Download More About MC Device Brochure 2 8 Mb Presentation Materials Examples

    Original URL path: http://www.silvaco.fr/products/vwf/atlas/2D/mc_device/mc_device_br.html (2016-05-03)
    Open archived version from archive

  • Giga - Non-Isothermal Device Simulator
    Power Devices Giga provides the capability to investigate design and optimize power devices Simulation of measurable electrical characteristics and conditions within the device that are temperature dependent provide critical insight into device behavior Probable failure mechanisms can be identified early in the process development cycle Temperature distribution in a Lateral DMOS transistor revealing a hot spot in the drift region Giga is used to locate and evaluate local heating effects during high current operation Location of the hot spot and current flow with the device in a latched state DC latchup characteristics as a function of gate voltage solved using a automatic curve tracing routine built into Atlas SOI Device Simulation Non isothermal effects are often important in silicon on insulator SOI devices because of the low thermal conductivity buried oxide Accurate characterization of drain current the kink effect and breakdown behavior of SOI devices requires non isothermal calculation Giga enables the analysis of the internal distributions of avalanche generation rates to assist in understanding thermal device performance effects Simulated I V curves for drift diffusion energy balance and non isothermal energy balance models Temperature distribution inside an SOI MOSFET and associated LOCOS isolations The device was defined using a LDD process sequence in Athena MOS Second Breakdown The thermally dominated second breakdown voltage in MOSFETs can be predicted using Giga An isothermal simulation under the same conditions fails to show the second breakdown The simulated DC results provided by Giga such as second breakdown voltages and trigger current are useful for determining ESD pulse tolerance Local Heating in GaAs MESFETs Temperature distribution within a GaAs MESFET during breakdown Non isothermal simulation is required to accurately characterize devices made from materials with low thermal conductivity substrates Rev 110113 04 Download More about Giga Brochure 1 5 MB Presentation Materials Examples

    Original URL path: http://www.silvaco.fr/products/vwf/atlas/giga/giga_br.html (2016-05-03)
    Open archived version from archive

  • MixedMode - Circuit Simulation for Advanced 2D Devices
    concentration within the physically based device can be examined at any time during the circuit transient This circuit is used to investigate GTO turn off The GTO is a physically based device whereas compact analytical models are used for the four diodes High Performance Digital Circuits High performance digital circuits can be simulated using physically based devices MixedMode provide accurate descriptions of charge storage and transit time effects This circuit is an ECL inverter Transistors Al and AN are simulated as physically based devices and transistors QI and QN are simulated using compact analytical models The calculated base and collector waveforms of the devices are shown below Precision Analog Circuits The algorithms used in Atlas device simulators provide complete charge conservation MixedMode is therefore able to simulate precision analog circuits This charge pump circuit provides a standard test of the ability of a device model to conserve charge The circuit is simulated using MixedMode with transistor A1 simulated as a physically based device The voltage waveform on the source of the MOS transistor node 5 has a steady DC level This demonstrates that charge is conserved Loaded Logic Circuits MixedMode makes it easy to simulate physically based devices with realistic circuit loads One application is determining Inverter switching speeds including the effects of parasitics and fan out The circuit above shows a CMOS inverter loaded by interconnect parasitics and another inverter Transistors AP and AN are simulated using physically based devices and transistors M1 and M2 are simulated using compact analytical models Conditions inside the two physically based devices The conditions inside multiple physically based devices can be displayed simultaneously Animation showing the evolution of internal conditions is easily generated Technical Specifications MixedMode circuits can include up to 200 nodes 300 elements and up to 10 physically based Atlas devices

    Original URL path: http://www.silvaco.fr/products/vwf/atlas/mmode/mmode_br.html (2016-05-03)
    Open archived version from archive

  • Ferro - Ferroelectric Field Dependent Permittivity Model
    of a ferroelectric material PZT normally sandwiched between two layers of silicon dioxide Ferro models the PZT material with a set of four material parameters the saturation polarization Ps the remanent polarization Pr the coercive field Ec and the linear dielectric constant epsf Ferro simulated a gate voltage sweep in both the positive and negative directions The Ferro model accounts for the ferroelectric polarization hysteresis phenomena which results in a shift on the observed threshold voltage depending upon the sweep direction A standard MFSFET structure which could be used as single transistor memory cell The gate stack is comprised of SiO2 and PZT ferroelectric materials Nonlinearities in the transient response of the MFSFET to a 1 MHz 4 volt sawtooth on the gate are shown Simulated unsaturated ferroelectric polarization curves for different drain bias values Simulation of Hysteresis The shape of the ferroelectric polarization curve is determined by the material parameter set Ps Pr Ec and eps To illustrate this we have simulated the MFSFET device with two parameter sets The simulation was done in the small signal ac domain so that the C V characteristics and polarization curves could both be shown These two figures show the polarization curve and resultant small signal C V results for the parameter set 1e 6 C cm 2 0 5e 6 C cm 2 20 kV cm 200 The gate bias was swept in both the positive and negative directions The Ferro parameter set was then changed to 1e 6 C cm 2 0 5e 6 C cm 2 50 kV cm 200 which has a higher coercive field This higher coercive field results in a broadening of the ferroelectric polarization curve as shown in the polarization curve above The resultant ferroelectric capacitance is shown beside it where we see lower values

    Original URL path: http://www.silvaco.fr/products/vwf/atlas/ferro/ferro_br.html (2016-05-03)
    Open archived version from archive